Various types of systems have been provided in the prior art for converting an analog voltage to digital signals (currents or voltages) representative of such analog voltage. One type of system often used in the prior art to provide such conversion has been known as a xe2x80x9cflash converterxe2x80x9d. In a flash converter, an analog input signal representative of the analog value to be converted digitally is introduced to a first input of a differential amplifier in each of a plurality of repetitive cells. An individual one of a plurality of progressive fractions in a reference voltage is introduced to a second input of such differential amplifier.
In the prior art, the differential amplifier in each cell may have first and second branches each including a transistor such as a CMOS transistor, each transistor having a gate, a source and a drain. The gates of the transistors in the first and second branches respectively receive the first and second inputs. The sources of the two (2) transistors in each differential amplifier have a common connection to a source of a substantially constant current. Load bearing currents flow through the transistors in the branches in each differential amplifier in accordance with the relative values of the voltages on the gates of the transistors, the sum of these currents being the substantially constant current.
Thus, a first output such as a binary xe2x80x9c1xe2x80x9d is produced in a comparator when the input voltage exceeds the particular fraction of the reference voltage introduced to the differential amplifier. Similarly, a second output such as a binary xe2x80x9c0xe2x80x9d is produced in the comparator when the input voltage is less than the particular fraction of the reference voltage introduced to the differential amplifier.
Exclusive xe2x80x9corxe2x80x9d networks compare the outputs from successive pairs of comparators. An output indication is provided by the exclusive xe2x80x9corxe2x80x9d network in which one of the comparator inputs is a binary xe2x80x9c1xe2x80x9d and the other input is a binary xe2x80x9c0xe2x80x9d. Each exclusive xe2x80x9corxe2x80x9d network is programmed to provide digital indications of the input voltage represented by such xe2x80x9corxe2x80x9d network.
The analog-to-digital converter discussed above is advantageous in that it can operate at high frequencies such as in the megahertz range. However, in order to determine the value of the input voltage with some accuracy and to convert this input voltage to the corresponding digital signals, a large number of amplifiers have to be provided. For example, for a converter providing a conversion of an analog signal to ten (10) binary bits, ten hundred and twenty four (1024) differential amplifiers and ten hundred and twenty three (1023) comparators would be required. When the input voltage is approximately two volts, each differential amplifier would have to provide a distinction between adjacent amplifiers in the order of two millivolts (2 mV.) Since this voltage is relatively small, it presents difficulties in the operation of the comparators.
The flash types of analog-to-digital converters have generally been disposed on an integrated circuit (IC) chip, particularly for a number of bits greater than about seven (7). Imperfections in the silicon substrate of the chip and in the methods of manufacturing the chip have produced mismatches between the outputs from successive pairs of differential amplifiers. These mismatches have caused errors to be produced in the stages providing the comparison between the input and reference voltages introduced to the differential amplifier. These mismatches have caused errors to be produced in the digital indications produced to represent the analog input signal.
Various attempts have been made to compensate for the cell mismatches produced in the converter of the prior art. For example, U.S. Pat. No. 5,175,550 issued to Kevin M. Kattman and Jeffrey G. Barrow for xe2x80x9cRepetitive Cell Matching Technique for Integrated Circuitsxe2x80x9d and assigned of record to Analog Devices, Inc. discloses a system for, and method of providing, such compensation. In the ""550 patent, a plurality of cells are provided each including a differential amplifier defined by two (2) branches. A transistor is provided in each branch. The transistor in a first one of the branches in each cell receives an input signal and the transistor in a second one of the branches in each cell receives an individual one of the progressive fractions of a reference voltage.
In the ""550 patent, a plurality of load resistors are provided each connected to an individual one of the transistors in one of the first and second branches in an individual one of the cells to receive the load current flowing through such transistor. In addition, a first plurality of averaging resistors is provided each connected between the corresponding output terminals of the transistors in the first branches of successive pairs of the repetitive cells. A second plurality of averaging resistors is also provided each connected between the corresponding output terminals of the transistors in the second branches of successive pairs of the repetitive cells.
The system disclosed in the ""550 patent operates to average the cell mismatches over a plurality of cells so as to reduce the inaccuracies resulting in the converted digital signals from the cell mismatches. Because of this, the system disclosed in the ""550 patent reduces the differential non-linearities and integral non-linearities in the analog-to-digital converter formed from the plurality of cells. The lower the values of the averaging resistors that are provided in the first and second pluralities in the ""550 patent, generally the greater is the improvement in the accuracy of the conversion from the analog value to the digital value. However, the gain in the system is reduced in the prior art when the values of the averaging resistors are reduced. Furthermore, the lower the gain, the more the offset in the comparators will become dominant. This limits the amount that the gain can be reduced in the prior art. Because of this, in the optimum, the differential non-linearity of the system disclosed in the ""550 patent is reduced by a factor of approximately three (3) (1.58 bits) in comparison to the A-D converters of the prior art.
Although the system disclosed in the ""550 patent provides a significant improvement in the accuracy of the digital output signals over the prior art, this improvement is small compared to the improvement produced in the accuracy of the output digital signals by the system disclosed and claimed in application Ser. No. 08/792,941 filed by Klaas Bult on Jan. 21, 1977, for an xe2x80x9cAnalog-to-Digital Converterxe2x80x9d and assigned of record to the assignee of record of this application. For example, the system disclosed and claimed in application Ser. No. 08/792,941 provides an improvement of the differential non-linearity in the accuracy of the output digital signals by as much as 17.3 (4 bits) when averaging over sixteen (16) stages was performed. The system disclosed and claimed in application Ser. No. 08/792,941 additionally averages currents from approximately sixteen (16) stages and produces an approximately two (2) binary bit gain in integral non-linearity.
In one embodiment of the invention disclosed and claimed in application Ser. No. 08/792,941, an analog-to-digital converter (ADC) formed on an integrated circuit chip from a plurality of cells includes a differential amplifier having first and second branches. The branches in each cell respectively have first and second transistors, one responsive to an input voltage and the other responsive to an individual one of progressive fractions of a reference voltage. The relative outputs from the branches for each cell are dependent upon the relative values of the two voltages introduced to the cell.
To minimize cell mismatches and the effects of these mismatches on cell outputs, first and second sets of averaging impedances, preferably resistors, are respectively connected in the system of application Ser. No. 08/792,941 between the output terminals of the first branch transistors, and between the output terminals of the second branch transistors, in successive pairs of cells.
Current sources connected to the output terminals of the transistors in the first and second branches in the system of application Ser. No. 08/792,941 have characteristics (preferably impedances approaching infinity) to force the signal bearing currents from the transistors to flow through the impedances in the first and second sets. The impedances have relatively low values, particularly in comparison to the impedances in the current sources, to reduce cell mismatches.
First and second resistive strips on the chip may be tapped at progressive positions in the system disclosed and claimed in application Ser. No. 08/792,941 to respectively define the impedances in the first and second sets. One end of each strip may be connected to the opposite end of the other strip to define a closed impedance loop and to minimize errors resulting from the averaging resistors at the ends of the strip.
The system disclosed and claimed in Ser. No. 08/792,941 application has certain important advantages over the prior art including the system of the ""550 patent. These advantages provide considerable improvements in differential non-linearity and integral non-linearity specified above. These considerable improvements result in part from the fact that the system of this invention uses current sources (of a very high impedance value) and further uses the averaging resistances with impedance values as the load elements whereas the ""550 patent uses resistors (not the averaging impedances) as the load devices.
The considerable improvements in the embodiment of the system disclosed and claimed in application Ser. No. 08/792,941 also result from the fact that the averaging impedances in the system of this invention constitute the actual signal current carrying load elements. In contrast, in the system of this invention, applicant provides a circular (or looped) termination of the averaging impedances. Furthermore, in the ""550 patent, the last resistors in the first and second pluralities are terminated on an open ended basis.
Although the system in application Ser. No. 08/792,941 is disclosed primarily for use in an analog-to-digital converter, it has utility in other systems as well. For example, the system disclosed in application Ser. No. 08/792,941 may be used in a digital-to-analog converter. Actually, the system may be used in any embodiment where a plurality of repetitive cells are provided, particularly when the repetitive cells are disposed on an integrated circuit chip.
In one embodiment of the invention, the output of each cell in an A-D converter in an IC chip is dependent upon the relative values of an input voltage and an individual one of progressive fractions of a reference voltage respectively introduced to the branches in a differential amplifier. To minimize output errors from cell mismatches, first and second sets of averaging impedances, preferably resistors, are respectively connected between the output terminals in the first branches, and the output terminals in the second branches, in successive pairs of cells. The impedances have relatively low values, particularly compared to the impedances of current sources connected to the branch output terminals.
First and second resistive strips on the chip may be tapped at progressive positions to respectively define the impedances in the first and second sets. One end of each strip may be connected to the opposite end of the other strip to define a closed impedance loop for minimizing averaging errors at the strip ends. Different fractions of the reference voltage are associated with each individual impedance in the first and second sets. Such reference voltage fractions associated with each individual impedance have a particular repetitive relationship.
In this way, the number of output terminals and cell mismatches are reduced. The different outputs at each individual impedance are determined for the progressive fractions of the reference voltage at such impedance. Successive voltage fractions for each impedance have opposite polarities to provide a folding relationship. Such outputs may be cascaded to further reduce cell mismatches and the number of output terminals.